Cortex-M: add explicit-layout runtime primitives - #22377
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/22377
Note: Links to docs will display an error until the docs builds have been completed. ✅ You can merge normally! (2 Unrelated Failures)As of commit 365c550 with merge base 1cfcdf8 ( FLAKY - The following job failed but was likely due to flakiness present on trunk:
BROKEN TRUNK - The following job failed but was present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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Define the experimental NHWC operator contracts and reference implementations needed by explicit-layout lowering. Add int8 transpose and contiguous padding support, and teach quantized add and multiply to execute flat channel broadcasts in either legacy channels-last storage or contiguous NHWC storage. Keep runtime shape and layout validation aligned with the AOT eligibility checks, and make pooling configuration and scratch sizing interpret dimensions through an explicit activation-layout contract. AI-assisted: Codex.
Add the pad_contiguous out schema to the generated operator library so serialized programs can resolve the C++ kernel introduced by the runtime foundation change. AI-assisted: Codex.
Repeat a scalar operand in a bounded stack tile so add and multiply retain CMSIS-NN quantization semantics without invoking the kernel once per output element. AI-assisted: Codex.
CMSIS-NN add and multiply accept equal-length vectors and do not expose broadcast-aware entry points. Follow the scalar-loop strategy used by its shape-aware min/max kernels instead of manufacturing repeated stack tiles, while continuing to use CMSIS-NN for non-scalar channel blocks.\n\nAI-assisted: Codex.
Remove the scalar-only add and multiply paths from this stack. Explicit layout only requires the existing per-channel CMSIS-NN loop to recognize contiguous NHWC operands; scalar broadcast performance is a separate concern and retains the legacy behavior.\n\nAI-assisted: Codex.
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Summary
Define the experimental NHWC operator contracts and reference implementations needed by explicit-layout lowering. Add and register the contiguous-padding runtime kernel, and allow the existing quantized add and multiply channel-broadcast path to operate on both legacy channels-last tensors and contiguous NHWC tensors.
Keep runtime shape and layout validation aligned with the AOT eligibility checks, and make pooling configuration and scratch sizing interpret dimensions through an explicit activation-layout contract.
Why these changes
Explicit layout stores NHWC tensors as ordinary contiguous tensors, so the legacy padding operator cannot infer the intended logical axes from dim order. A distinct
pad_contiguouscontract makes that difference visible and is registered here alongside its C++ implementation.Quantized add and multiply already support a per-channel CMSIS-NN loop when the broadcast operand is contiguous in physical memory. The implementation previously identified the loop length through the legacy logical channel axis. This PR instead derives it from the broadcast operand itself, allowing the same path to serve contiguous NHWC tensors while preserving legacy behavior. General and scalar broadcasting remain out of scope.
The remaining NHWC schemas establish Python fake and reference contracts for the following kernel PRs. Their runtime registrations land with their C++ implementations so each kernel PR is independently executable.
AI-assisted: Codex.
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