ISLE: Veri: include counterexample in CI log for failures

[avanhatt]

Include counterexamples when verification fails in the CI log (capped at 25 total).

For example, failure log now includes:

==========================
Cache mode:         ReadWrite
Cache source:       cranelift/isle/veri/cache
Cache destination:  cranelift/isle/veri/cache.rebuild
=== VERIFICATION FAILURES (4) ===
FAILURE #4	cranelift/codegen/src/opts/arithmetic.isle line 23	(instantiation 0)	.veriisle/expansions/00004/000/failure.out
#4	cranelift/codegen/src/opts/arithmetic.isle line 23	instantiation=0
model:
state: relax_nan = false
state: clif_trap = false
state: clif_load = {active: false, size_bits: 0, addr: #x0000000000000000}
state: clif_store = {active: false, size_bits: 1, addr: #x0000000000000000, value: #x0000000000000000}
state: loaded_value = #x0000000000000000
iadd({bits: 8}, #x40, #xdf) -> #x1f
ineg({bits: 8}, #x21) -> #xdf
isub({bits: 8}, #x21, #x40) -> #xe1
simplify(#x1f) -> #xe1

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cc @avanhatt, @cfallin, @fitzgen, @mmcloughlin

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[cfallin]

Thanks! Looks like a submodule change to tests/component-model got caught in the diff too (git submodule update before committing, I often forget too...) -- happy to merge once that's fixed!