make assert_instr total instruction limit configurable per-test

Author: RalfJung

crates/assert-instr-macro/src/lib.rs

@@ -36,6 +36,11 @@ pub fn assert_instr(
 
     let instr = &invoc.instr;
     let not = invoc.not;
+    let limit = match invoc.limit {
+        None => quote! { None },
+        Some(l) => quote! { Some(#l) },
+    };
+
     let name = &func.sig.ident;
     let maybe_allow_deprecated = if func
         .attrs
@@ -180,7 +185,7 @@ pub fn assert_instr(
         fn #assert_name() {
             #to_test
 
-            ::stdarch_test::assert(#shim_name as usize, stringify!(#shim_name), #instr, &[#(#not),*]);
+            ::stdarch_test::assert(#shim_name as usize, stringify!(#shim_name), #instr, &[#(#not),*], #limit);
         }
     };
 
@@ -194,6 +199,7 @@ pub fn assert_instr(
 struct Invoc {
     instr: String,
     not: Vec<String>,
+    limit: Option<syn::LitInt>,
     args: Vec<(syn::Ident, syn::Expr)>,
 }
 
@@ -229,6 +235,7 @@ impl syn::parse::Parse for Invoc {
 
         let instr = parse_instr(input)?;
         let mut not = Vec::new();
+        let mut limit = None;
         let mut args = Vec::new();
 
         while !input.is_empty() {
@@ -237,8 +244,8 @@ impl syn::parse::Parse for Invoc {
                 return Err(input.error("extra tokens at end"));
             }
 
-            // This is either `not(instr)` or `arg = val`.
-            // We treat `not` as a magic identifier here.
+            // This is either `not(instr)` or `limit(n)` or `arg = val`.
+            // We treat `not` and `limit` as a magic identifier here.
 
             let name = input.parse::<syn::Ident>()?;
 
@@ -252,12 +259,24 @@ impl syn::parse::Parse for Invoc {
                 not.push(not_instr);
                 continue;
             }
+            if name == "limit" {
+                let content;
+                parenthesized!(content in input);
+                let n = content.parse::<syn::LitInt>()?;
+                limit = Some(n);
+                continue;
+            }
 
             input.parse::<Token![=]>()?;
             let expr = input.parse::<syn::Expr>()?;
             args.push((name, expr));
         }
-        Ok(Self { instr, not, args })
+        Ok(Self {
+            instr,
+            not,
+            limit,
+            args,
+        })
     }
 }
 

crates/core_arch/src/x86/avx2.rs

@@ -2321,7 +2321,7 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi16)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpacksswb))]
+#[cfg_attr(test, assert_instr(vpacksswb, limit(2)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(packsswb(a.as_i16x16(), b.as_i16x16())) }
@@ -2333,7 +2333,7 @@ pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi32)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpackssdw))]
+#[cfg_attr(test, assert_instr(vpackssdw, limit(2)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(packssdw(a.as_i32x8(), b.as_i32x8())) }
@@ -2345,7 +2345,7 @@ pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi16)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpackuswb))]
+#[cfg_attr(test, assert_instr(vpackuswb, limit(2)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(packuswb(a.as_i16x16(), b.as_i16x16())) }
@@ -2357,7 +2357,7 @@ pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi32)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpackusdw))]
+#[cfg_attr(test, assert_instr(vpackusdw, limit(2)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(packusdw(a.as_i32x8(), b.as_i32x8())) }

crates/core_arch/src/x86/sse2.rs

@@ -1496,7 +1496,7 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi16)
 #[inline]
 #[target_feature(enable = "sse2")]
-#[cfg_attr(test, assert_instr(packsswb, not(pminsw), not(pmaxsw)))]
+#[cfg_attr(test, assert_instr(packsswb, limit(2)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(packsswb(a.as_i16x8(), b.as_i16x8())) }
@@ -1508,7 +1508,7 @@ pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi32)
 #[inline]
 #[target_feature(enable = "sse2")]
-#[cfg_attr(test, assert_instr(packssdw))]
+#[cfg_attr(test, assert_instr(packssdw, limit(2)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(packssdw(a.as_i32x4(), b.as_i32x4())) }
@@ -1520,7 +1520,7 @@ pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi16)
 #[inline]
 #[target_feature(enable = "sse2")]
-#[cfg_attr(test, assert_instr(packuswb, not(pminsw), not(pmaxsw)))]
+#[cfg_attr(test, assert_instr(packuswb, limit(2)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(packuswb(a.as_i16x8(), b.as_i16x8())) }

crates/stdarch-test/src/lib.rs

@@ -54,7 +54,7 @@ impl hash::Hash for Function {
 ///
 /// This asserts that the function at `fnptr` contains the instruction
 /// `expected` provided.
-pub fn assert(shim_addr: usize, fnname: &str, expected: &str, not: &[&str]) {
+pub fn assert(shim_addr: usize, fnname: &str, expected: &str, not: &[&str], limit: Option<usize>) {
     // Make sure that the shim is not removed
     black_box(shim_addr);
 
@@ -131,68 +131,67 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str, not: &[&str]) {
 
     let instruction_limit = std::env::var("STDARCH_ASSERT_INSTR_LIMIT")
         .ok()
-        .map_or_else(
-            || match expected {
-                // `cpuid` returns a pretty big aggregate structure, so exempt
-                // it from the slightly more restrictive 22 instructions below.
-                "cpuid" => 30,
-
-                // These require 8 loads and stores, so it _just_ overflows the limit
-                "aesencwide128kl" | "aesencwide256kl" | "aesdecwide128kl" | "aesdecwide256kl" => 24,
-
-                // Apparently, on Windows, LLVM generates a bunch of
-                // saves/restores of xmm registers around these instructions,
-                // which exceeds the limit of 20 below. As it seems dictated by
-                // Windows's ABI (I believe?), we probably can't do much
-                // about it.
-                "vzeroall" | "vzeroupper" if cfg!(windows) => 30,
-
-                // Intrinsics using `cvtpi2ps` are typically "composites" and
-                // in some cases exceed the limit.
-                "cvtpi2ps" => 25,
-                // core_arch/src/arm_shared/simd32
-                // vfmaq_n_f32_vfma : #instructions = 26 >= 22 (limit)
-                "usad8" | "vfma" | "vfms" => 27,
-                "qadd8" | "qsub8" | "sadd8" | "sel" | "shadd8" | "shsub8" | "usub8" | "ssub8" => 29,
-                // core_arch/src/arm_shared/simd32
-                // vst1q_s64_x4_vst1 : #instructions = 27 >= 22 (limit)
-                "vld3" => 28,
-                // core_arch/src/arm_shared/simd32
-                // vld4q_lane_u32_vld4 : #instructions = 36 >= 22 (limit)
-                "vld4" => 37,
-                // core_arch/src/arm_shared/simd32
-                // vst1q_s64_x4_vst1 : #instructions = 40 >= 22 (limit)
-                "vst1" => 41,
-                // core_arch/src/arm_shared/simd32
-                // vst3q_u32_vst3 : #instructions = 25 >= 22 (limit)
-                "vst3" => 26,
-                // core_arch/src/arm_shared/simd32
-                // vst4q_u32_vst4 : #instructions = 33 >= 22 (limit)
-                "vst4" => 34,
-
-                // core_arch/src/arm_shared/simd32
-                // vst1q_p64_x4_nop : #instructions = 33 >= 22 (limit)
-                "nop" if fnname.contains("vst1q_p64") => 34,
-
-                // AMX intrinsics generate a lot of move instructions to load/store the tile registers
-                // due to Rust ABI
-                _ if fnname.contains("___tile") => 165,
-
-                // Original limit was 20 instructions, but ARM DSP Intrinsics
-                // are exactly 20 instructions long. So, bump the limit to 22
-                // instead of adding here a long list of exceptions.
-                _ => {
-                    // aarch64_be may add reverse instructions which increases
-                    // the number of instructions generated.
-                    if cfg!(all(target_endian = "big", target_arch = "aarch64")) {
-                        32
-                    } else {
-                        22
-                    }
+        .map(|v| v.parse().unwrap())
+        .or(limit.map(|n| n + 1)) // adjust for the `<` below: `limit = 2` means 2 instructions is okay
+        .unwrap_or_else(|| match expected {
+            // `cpuid` returns a pretty big aggregate structure, so exempt
+            // it from the slightly more restrictive 22 instructions below.
+            "cpuid" => 30,
+
+            // These require 8 loads and stores, so it _just_ overflows the limit
+            "aesencwide128kl" | "aesencwide256kl" | "aesdecwide128kl" | "aesdecwide256kl" => 24,
+
+            // Apparently, on Windows, LLVM generates a bunch of
+            // saves/restores of xmm registers around these instructions,
+            // which exceeds the limit of 20 below. As it seems dictated by
+            // Windows's ABI (I believe?), we probably can't do much
+            // about it.
+            "vzeroall" | "vzeroupper" if cfg!(windows) => 30,
+
+            // Intrinsics using `cvtpi2ps` are typically "composites" and
+            // in some cases exceed the limit.
+            "cvtpi2ps" => 25,
+            // core_arch/src/arm_shared/simd32
+            // vfmaq_n_f32_vfma : #instructions = 26 >= 22 (limit)
+            "usad8" | "vfma" | "vfms" => 27,
+            "qadd8" | "qsub8" | "sadd8" | "sel" | "shadd8" | "shsub8" | "usub8" | "ssub8" => 29,
+            // core_arch/src/arm_shared/simd32
+            // vst1q_s64_x4_vst1 : #instructions = 27 >= 22 (limit)
+            "vld3" => 28,
+            // core_arch/src/arm_shared/simd32
+            // vld4q_lane_u32_vld4 : #instructions = 36 >= 22 (limit)
+            "vld4" => 37,
+            // core_arch/src/arm_shared/simd32
+            // vst1q_s64_x4_vst1 : #instructions = 40 >= 22 (limit)
+            "vst1" => 41,
+            // core_arch/src/arm_shared/simd32
+            // vst3q_u32_vst3 : #instructions = 25 >= 22 (limit)
+            "vst3" => 26,
+            // core_arch/src/arm_shared/simd32
+            // vst4q_u32_vst4 : #instructions = 33 >= 22 (limit)
+            "vst4" => 34,
+
+            // core_arch/src/arm_shared/simd32
+            // vst1q_p64_x4_nop : #instructions = 33 >= 22 (limit)
+            "nop" if fnname.contains("vst1q_p64") => 34,
+
+            // AMX intrinsics generate a lot of move instructions to load/store the tile registers
+            // due to Rust ABI
+            _ if fnname.contains("___tile") => 165,
+
+            // Original limit was 20 instructions, but ARM DSP Intrinsics
+            // are exactly 20 instructions long. So, bump the limit to 22
+            // instead of adding here a long list of exceptions.
+            _ => {
+                // aarch64_be may add reverse instructions which increases
+                // the number of instructions generated.
+                if cfg!(all(target_endian = "big", target_arch = "aarch64")) {
+                    32
+                } else {
+                    22
                 }
-            },
-            |v| v.parse().unwrap(),
-        );
+            }
+        });
     let probably_only_one_instruction = instrs.len() < instruction_limit;
 
     if found && found_bad.is_none() && probably_only_one_instruction && !inlining_failed {